Recordable disk recording controller with batch register controller

ABSTRACT

In a recordable disk recording controller circuit, a data buffer manager receives a command and sends the command to a micro-controller. The micro-controller generates a set of register batches from each command and sends the register data and index of the register batch to a batch register controller. The batch register controller receives the register data and index of the register batch from the micro-controller and stores the received register data and index of the register batch in a batch buffer. The batch register controller retrieves the register batches from the batch buffer and writes the master registers of an encoder controller based on the register index and register data of the register batches after the master registers of the encoder controller are updated into the slave registers of the encoder controller. The encoder controller generates control signals to a recording circuit depending on updated slave registers. Such control signals cause the recording circuit to record a signal representative of signal data on a recordable disk located in a recordable disk driver.

BACKGROUND OF THE INVENTION

[0001] A. Field of the Invention

[0002] The present invention relates to a recordable disk recordingcontroller for use in a multi-media computer system. More particularly,the present invention relates to a recordable compact disk(CD-R)/rewritable compact disk (CD-RW) recording controller with a batchregister controller for improving the rate of recording a signalrepresentative of signal data on a CD-R/CD-RW disk.

[0003] B. Description of the Related Art

[0004] Conventional multi-media computer systems include a CD-R/CD-RWdriver for recording multi-media signals on a CD-R/CD-RW disk. Oneexample of the conventional multi-media computer systems is described inthe U.S. Pat. No. 5,940,358, which is cited in the following withreference to FIGS. 1(a) and 1(b).

[0005]FIG. 1(a) is a block diagram showing a conventional multi-mediacomputer system 10 including a host processor 11, a CD-R/CD-RWcontroller 12, a micro-controller 13, a buffer 14, a CD-R/CD-RW driver15, a ROM 16, and a RAM 17. FIG. 1(b) is a flow-chart illustrating themethod employed by the conventional multi-media computer system 10 forrecording a signal representative of signal data on a CD-R/CD-RW disk(not shown). The host processor 11 comprises a central processing unitto send a multi-media signal, encoded as signal data, and commands tospecify information required for recording the signal.

[0006] The CD-R/CD-RW controller 12 receives signal data (step 110 shownin FIG. 1(b)) and commands from the host processor 11, and generatesrecording signals to record on the CD-R/CD-RW disk a signalrepresentative of signal data. The CD-R/CD-RW controller 12 sends thecommands to the micro-controller 13, which in turn generates a set ofcontrol signals to cause the CD-R/CD-RW controller 12 to record on theCD-R/CD-RW disk a signal representative of signal data. The CD-R/CD-RWcontroller 12 stores in the buffer 14 signal data received from the hostprocessor 11. In response to control signals generated by themicro-controller 13, the CD-R/CD-RW controller 12 retrieves signal datafrom the buffer 14 and generates recording signals to record a signalrepresentative of signal data on the CD-R/CD-RW disk located in theCD-R/CD-RW driver 15.

[0007] To generate such control signals, the micro-controller 13generates a table corresponding to each command (step 120 shown in FIG.1(b)) and generates control signals from the table. The ROM 16 storesinformation used to generate such table, and the micro-controller 13accordingly accesses the ROM 16 to generate the table corresponding to acommand. A table contains information necessary for encoding signal dataon several sectors during a recording operation.

[0008] In the conventional multi-media computer system, themicro-controller 13 stores in the RAM 17 a table generated correspondingto each command (step 130 shown in FIG. 1(b)). The micro-controller 13then accesses such a table from the RAM 17, and generates controlsignals to the CD-R/CD-RW controller 12 using information in the table(step 140 shown in FIG. 1(b)). Due to such access, the micro-controller13 potentially accesses the RAM 17 to generate control signals forrecording signal data on each sector.

[0009] One problem with such a conventional multi-media computer system10 is that the micro-controller 13 may not have enough throughputperformance to support high-speed recording requirements of currentcomputer systems because the micro-controller 13 may make a high numberof accesses to the RAM 17 for accessing information in a table.

[0010] Due to the throughput performance problems and consequentinability to generate control signals at a sufficient speed, themicro-controller 13 may fail to generate control signals at acorresponding rate at which signal data is received by the CD-R/CD-RWcontroller 12. Due to such failure, the CD-R/CD-RW controller 12 missesrecording a portion of signal data on the CD-R/CD-RW disk located inCD-R/CD-RW driver 15. The quality of recorded signals therefore isunacceptable.

SUMMARY OF THE INVENTION

[0011] In view of the above-described drawbacks of the conventionalCD-R/CD-RW recording controller, an object of the present invention isto provide a recordable disk recording controller that improves thecommunication efficiency between the encoder controller and themicro-controller. As a result, the recordable disk recording controlleraccording to the present invention never misses recording signal dataand achieves the acceptable quality of recoded signals.

[0012] Another object of the present invention is to provide a computersystem equipped with a recordable disk recording controller whosethroughput performance is enhanced. As a result, the recordable diskrecording controller according to the present invention is not aperformance bottleneck as in the conventional multi-media computersystem during a recording operation.

[0013] According to the present invention, a recordable disk recordingcontroller comprises a host interface for receiving a set of signal dataand a command from a host processor. A data buffer manager receives thesignal data and the command from the host interface and sends thecommand to a micro-controller. The micro-controller generates a set ofregister batches from each command and sends the register data and indexof the register batch to a batch register controller. The batch registercontroller receives the register data and index of the register batchfrom the micro-controller and stores the received register data andindex of the register batch in a batch buffer.

[0014] Moreover, the batch register controller retrieves the registerbatches from the batch buffer and writes the master registers of aencoder controller based on the register index and register data of theregister batches after the master registers of the encoder controllerare updated into the slave registers of the encoder controller. Theslave registers of the encoder controller are updated after finishingwhat should be done according to previous slave registers. The encodercontroller generates control signals to a recording circuit depending onupdated slave registers. Such control signals cause the recordingcircuit to record a signal representative of signal data on a recordabledisk located in a recordable disk driver.

[0015] Therefore, the micro-controller only needs to send the registerdata that should be changed. Since the number of data sent by themicro-controller is fewer than the prior art, the present inventionimproves the communication efficiency between the encoder controller andthe micro-controller.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above-mentioned and other objects, features, and advantagesof the present invention will become apparent with reference to thefollowing detailed descriptions and accompanying drawings, wherein:

[0017]FIG. 1 (a) is a block diagram showing a conventional multi-mediacomputer system, while FIG. 1(b) is a flow chart illustrating a methodemployed by the conventional multi-media computer system for recording asignal representative of signal data on a recordable disk;

[0018]FIG. 2(a) is a block diagram showing a multi-media computer systemaccording to a first embodiment of the present invention including abatch register controller and a batch buffer;

[0019]FIG. 2(b) is a flow chart illustrating a method employed by themulti-media computer system of FIG. 2(a) for recording a signalrepresentative of signal data on a recordable disk;

[0020]FIG. 2(c) is a block diagram showing a batch register controllerin the multi-media computer system of FIG. 2(a); and

[0021]FIG. 3(a) is a block diagram showing a multi-media computer systemaccording to a second embodiment of the present invention, while FIG.3(b) is a block diagram showing a batch register controller in themulti-media computer system of FIG. 3(a).

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The preferred embodiments according to the present invention willbe described in detail with reference to the drawings.

[0023] Referring to FIGS. 2(a) and 2(b), a recordable disk controller 20according to a first embodiment of the present invention performs arecording function based on a flow chart shown in FIG. 2(b), therebyrecording a signal representative of a set of signal data on arecordable disk, such as a CD-R or a CD-RW. A host interface 21 receivessignal data and commands from a host processor 22 in step 210. Thereceived commands include CUE-sheet commands that are well known in theindustry. The host interface 21 uses a conventional standard such as asmall computers systems interface (SCSI) or ATAPI to receive commandsand data from the host processor 22.

[0024] A data buffer manager 23 receives commands and signal data fromthe host interface 21, and then stores the received signal data in adata buffer 24. The data buffer manager 23 according to the firstembodiment of the present invention further sends the commands to amicro-controller 25 in step 220. Next in step 230, the micro-controller25 generates a set of register batches corresponding to each command.

[0025] Subsequently, the micro-controller 25 sends the register data andindex of the register batch to a batch register controller 26 in step240. Hence, the micro-controller 25 according to the present inventiondoes not generate all control signals to store in its local RAM (notshown) and then send what is required to the recordable disk controller20 as in the prior art, but merely sends the register data and index ofthe register batch to the batch register controller 26 instead. As themicro-controller 25 does not fetch such control signals from its localRAM when they are required urgently, the micro-controller 25 is nolonger a performance bottleneck in the computer system as in the priorart.

[0026] The batch register controller 26 receives the register data andindex of the register batch from the micro-controller 25, and thenstores the received register data and index of the register batch in abatch buffer 27 in step 250. According to the present invention, anencoder controller 28 controlled by internal controller registers isprovided in the recordable disk controller 20. Therefore in step 260,the batch register controller 26 retrieves the register batches from thebatch buffer 27 and writes the master registers of an encoder controller28 based on the register index and register data of the register batchesafter the master registers of the encoder controller 28 are updated intothe slave registers of the encoder controller 28.

[0027] Referring to step 270, the slave registers of the encodercontroller 28 are updated after finishing what should be done accordingto previous slave registers. Next in step 280, the encoder controller 28generates control signals to a recording circuit 29 depending on updatedslave registers. Such control signals cause the recording circuit 29 torecord a signal representative of signal data on a recordable disk (notshown) located in a recordable disk driver 30. As described above, therecordable disk may be a CD-R, a CD-RW, or the like. More specifically,the recording circuit 29 includes a servo controller, an EFM modulationfunction, and an interface with the recordable disk driver 30 and iscontrolled by the encoder controller 28 to do C1, C2, and C3 encoding.

[0028]FIG. 2(c) is a block diagram showing the batch register controlleraccording to the first embodiment of the present invention. The batchregister controller 26 includes a register write circuit 261, a batchcontroller circuit 262, and a direct memory access (DMA) controllercircuit 263. The register write circuit 261 is coupled to themicro-controller 25 for receiving a set of encoder controller registerprogramming batches from the micro-controller 25. The batch controllercircuit 262 is coupled to the encoder controller 28 for updating theregisters of the batch controller circuit 262 upon being allowed by theencoder controller 28. The DMA controller circuit 263 is coupled to theregister write circuit 261, the batch controller circuit 262, and thebatch buffer 27. The DMA controller circuit 263 receives the requestfrom the micro-controller 25 to write the data of the programming batchthrough the data buffer manager 23, and then stores the receivedregister data and index of the register batch in the batch buffer 27. Inaddition, the DMA controller circuit 263 receives the request from thebatch controller circuit 262 to read the data of the programming batchthrough the data buffer manager 23.

[0029]FIG. 3(a) is a block diagram showing a multi-media computer systemaccording to a second embodiment of the present invention. The secondembodiment differs from the first embodiment in the arrangement of thebatch buffer 27. More specifically, the batch buffer in the secondembodiment is incorporated with the data buffer 24. Therefore, thesecond embodiment saves the space occupied by the recordable diskcontroller 20.

[0030]FIG. 3(b) is a block diagram showing the batch register controlleraccording to the second embodiment of the present invention. The batchregister controller 26 includes a register write circuit 261, a batchcontroller circuit 262, and a DMA controller circuit 263. The registerwrite circuit 261 is coupled to the micro-controller 25 for receiving aset of encoder controller register programming batches from themicro-controller 25. The batch controller circuit 262 is coupled to theencoder controller 28 for updating the registers of the batch controllercircuit 262 upon being allowed by the encoder controller 28. The DMAcontroller circuit 263 is coupled to the register write circuit 261, thebatch controller circuit 262, and the data buffer manager 23. The DMAcontroller circuit 263 receives the request from the micro-controller 25to write the data of the programming batch through the data buffermanager 23. In addition, the DMA controller circuit 263 receives therequest from the batch controller circuit 262 to read the data of theprogramming batch through the data buffer manager 23.

[0031] According to the present invention, the micro-controller sendsthe register data and index of the register batch to the batch buffer,and then the batch buffer writes the register data and index of theregister batch into the encoder controller. Therefore, themicro-controller only needs to send the register data that should bechanged. The present invention successfully improves the communicationefficiency between the encoder controller and the micro-controller.

[0032] While the invention has been described by way of example and interms of the preferred embodiment, it is to be understood that theinvention is not limited to the disclosed embodiment. To the contrary,it is intended to cover various modifications and similar arrangementsas would be apparent to those skilled in the art. Therefore, the scopeof the appended claims should be accorded the broadest interpretation soas to encompass all such modifications and similar arrangements.

What is claimed is:
 1. A recordable disk controller for use in a computer system to record a signal representative of a set of signal data on a recordable disk, the recordable disk controller comprising: a host interface circuit for receiving the set of signal data and a command from a host processor comprised in the computer system; a data buffer manager coupled to said host interface circuit, said data buffer manager sending the command to a micro-controller comprised in the computer system, the micro-controller for generating a set of encoder controller register programming batches corresponding to the command; a batch register controller coupled to said micro-controller, said batch register controller receiving the set of encoder controller register programming batches from said micro-controller; a batch buffer coupled to said batch register controller, said batch buffer receiving and storing the set of encoder controller register programming batches from said batch register controller; a recording circuit for generating a set of recording signals for recording on said recordable disk the signal representative of the set of signal data; and an encoder controller circuit coupled to said recording circuit and said batch register controller, said encoder controller circuit generating a set of control signals, wherein the set of control signals cause said recording circuit to generate the set of recording signals.
 2. A recordable disk controller according to claim 1, wherein said batch register controller comprising: a register write circuit coupled to said micro-controller, said register write circuit receiving the set of encoder controller register programming batches from said micro-controller; a batch controller circuit coupled to said encoder controller, said batch controller updating the registers of said batch controller circuit upon being allowed by said encoder controller; and a DMA controller circuit coupled to said register write circuit, said batch buffer, and said batch controller circuit, said DMA controller circuit receiving a request from said micro-controller to write the data of the programming batch into said batch buffer, said DMA controller circuit receiving a request from said batch controller circuit to read the data of the programming batch from said batch buffer.
 3. A recordable disk controller for use in a computer system to record a signal representative of a set of signal data on a recordable disk, the recordable disk controller comprising: a host interface circuit for receiving the set of signal data and a command from a host processor comprised in the computer system; a data buffer manager coupled to said host interface circuit, said data buffer manager sending the command to a micro-controller comprised in the computer system, the micro-controller for generating a set of encoder controller register programming batches corresponding to the command; a batch register controller coupled to said micro-controller and said data buffer manager, said batch register controller receiving the set of encoder controller register programming batches from said micro-controller, said batch register controller sending the set of encoder controller register programming batches to said data buffer manager; a recording circuit for generating a set of recording signals for recording on said recordable disk the signal representative of the set of signal data; and an encoder controller circuit coupled to said recording circuit and said batch register controller, said encoder controller circuit generating a set of control signals, wherein the set of control signals cause said recording circuit to generate the set of recording signals.
 4. A recordable disk controller according to claim 3, wherein said batch register controller comprising: a register write circuit coupled to said micro-controller, said register write circuit receiving the set of encoder controller register programming batches from said micro-controller; a batch controller circuit coupled to said encoder controller, said batch controller circuit updating the registers of said batch controller circuit upon being allowed by said encoder controller; and a DMA controller circuit coupled to said register write circuit, said data buffer manager, and said batch controller circuit, said DMA controller circuit receiving a request from said micro-controller to write the data of the programming batch through said data buffer manager, said DMA controller circuit receiving a request from said batch controller circuit to read the data of the programming batch through said data buffer manager.
 5. A computer system for recording on a recordable disk a signal representative of a set of signal data according to a command, the computer system comprising: a host processor for sending the set of signal data; a recordable disk driver for receiving said recordable disk; a micro-controller for generating a set of encoder controller register programming batches corresponding to the command; a buffer for storing a set of recording data; and a recordable disk controller for generating a set of control signals to cause said recordable disk driver to record the signal on said recordable disk, said recordable disk controller receiving the set of signal data and the command from said host processor, said recordable disk controller comprising: a host interface circuit for receiving the set of signal data and the command from said host processor comprised in the computer system; a data buffer manager coupled to said host interface circuit, said data buffer manager sending the command to said micro-controller comprised in the computer system, said micro-controller for generating a set of encoder controller register programming batches corresponding to the command; a batch register controller coupled to said micro-controller, said batch register controller receiving the set of encoder controller register programming batches from said micro-controller; a batch buffer coupled to said batch register controller, said batch buffer receiving and storing the set of encoder controller register programming batches from said batch register controller; a recording circuit for generating a set of recording signals for recording on said recordable disk the signal representative of the set of signal data; and an encoder controller circuit coupled to said recording circuit and said batch register controller, said encoder controller circuit generating a set of control signals, wherein the set of control signals cause said recording circuit to generate the set of recording signals.
 6. A computer system according to claim 5, wherein said batch register controller comprising: a register write circuit coupled to said micro-controller, said register write circuit receiving the set of encoder controller register programming batches from said micro-controller; a batch controller circuit coupled to said encoder controller, said batch controller updating the registers of said batch controller circuit upon being allowed by said encoder controller; and a DMA controller circuit coupled to said register write circuit, said batch buffer, and said batch controller circuit, said DMA controller circuit receiving a request from said micro-controller to write the data of the programming batch into said batch buffer, said DMA controller circuit receiving a request from said batch controller circuit to read the data of the programming batch from said batch buffer.
 7. A computer system for recording on a recordable disk a signal representative of a set of signal data according to a command, the computer system comprising: a host processor for sending the set of signal data; a recordable disk driver for receiving said recordable disk; a micro-controller for generating a set of encoder controller register programming batches corresponding to the command; a buffer for storing the set of encoder controller register programming batches and for storing a set of recording data; and a recordable disk controller for generating a set of control signals to cause said recordable disk driver to record the signal on said recordable disk, said recordable disk controller receiving the set of signal data and the command from said host processor, said recordable disk controller comprising: a host interface circuit for receiving the set of signal data and the command from said host processor comprised in the computer system; a data buffer manager coupled to said host interface circuit, said data buffer manager sending the command to said micro-controller comprised in the computer system, said micro-controller for generating a set of encoder controller register programming batches corresponding to the command; a batch register controller coupled to said micro-controller and said data buffer manager, said batch register controller receiving the set of encoder controller register programming batches from said micro-controller, said batch register controller sending the set of encoder controller register programming batches to said data buffer manager; a recording circuit for generating a set of recording signals for recording on said recordable disk the signal representative of the set of signal data; and an encoder controller circuit coupled to said recording circuit and said batch register controller, said encoder controller circuit generating a set of control signals, wherein the set of control signals cause said recording circuit to generate the set of recording signals.
 8. A computer system according to claim 7, wherein said batch register controller comprising: a register write circuit coupled to said micro-controller, said register write circuit receiving the set of encoder controller register programming batches from said micro-controller; a batch controller circuit coupled to said encoder controller, said batch controller updating the registers of said batch controller circuit upon being allowed by said encoder controller; and a DMA controller circuit coupled to said register write circuit, said data buffer manager, and said batch controller circuit, said DMA controller circuit receiving a request from said micro-controller to write the data of the programming batch through said data buffer manager, said DMA controller circuit receiving a request from said batch controller circuit to read the data of the programming batch through said data buffer manager. 